Integrated circuit chips are complex, typically highly miniaturized electronic circuits that can be designed to perform a wide variety of functions in electronics of nearly every kind. See an integrated circuit chip shown in FIG. 1 for example. Differing integrated chips include differing electrical components such as transistors, resistors, capacitors and diodes connected to each other in different ways. These components have differing behaviors, and assembling these differing components in myriad differing ways on chips yields similarly differing electronic functions performed by the differing chips.
As a result, integrated chips have become ubiquitous in electronics of nearly every type in the modern industrialized world. Consequently, the size of the worldwide integrated chip market has long been enormous.
Integrated chips are, however, difficult to manufacture, requiring super clean manufacturing environments and equipment. As these chips are manufactured, they too must be maintained in a super clean condition. The chip manufacturing process, however, necessarily leads to contamination of the chip manufacturing apparatus, which leads to contamination of the manufactured chips. This contamination can and often does damage or even ruin the resulting chips. Consequently, the chip manufacturing industry has long been engaged in seeking more effective, more efficient, and less costly techniques for maintaining a super clean environment during manufacturing of integrated circuit chips. See, e.g., U.S. Pat. No. 6,777,966 to Humphrey et al., which is hereby incorporated by reference.
In this regard, chips are commonly manufactured on “stages” in the chip manufacturing apparatus. Differing stages are used to form differing portions of electronic circuitry components on the wafer. See, e.g., U.S. Pat. No. 6,256,555 to Bacchi et al, U.S. Pat. No. 6,155,768 to Bacchi et al. A stage can often have a complex surface structure, including burls, flat areas, vacuum ports, and other structures. Id
During wafer manufacturing, small particulate contaminate debris builds up on the equipment and the stages. For example, the build-up of particulate contaminants on stages can affect the focus and accuracy of the photolithography process during chip circuit production. Removing contaminants from the crevices, valleys, and other surface structure on the surface of the various stages and wafer handling equipment has long presented a substantial challenge.
Offline cleaning of stages and handling equipment commonly requires tool downtime and opening of the automated wafer handling equipment. The integrated circuit manufacturer incurs a significant cost as equipment downtime for this cleaning operation lowers production throughput.
In-line cleaning techniques have sought to avoid the need to shut down the wafer processing tool and to increase production efficiency and yield of integrated circuit wafers. One in-line cleaning technique has involved using a non-tacky polyimide surface on a cleaning wafer to collect debris via static charge on the wafer manufacturing stages and manufacturing apparatus. See, e.g., processes of such companies as Nitto Denko, Metron Technology, and Applied Materials. Other in-line cleaning techniques have utilized generally planar wafers or wafers with slight surface roughness produced with viscoelastic, polymers such as silicone (e.g., see additional processes of Nitto Denko, Metron Technologies, and Applied Materials).
Typically, the cleaning wafer substrates of the prior art have not had sufficient surface adhesion, or “tackiness,” to achieve the desired level of debris collection. The reason for this short-coming is that if the level of surface adhesion is sufficient to remove the majority of the foreign particulates in a prior art planar wafer, the adhesion between the cleaning surface and the contact surfaces of the hardware often has prevented adequate release and removal of the cleaning wafer from manufacturing hardware, wafer stages, or chucks.
Consequently, the prior art cleaning wafers have typically been designed with limited or no tack, the result being that the use of a cleaning wafer in a planar wafer substrate without adhesive properties or insufficient adhesive properties typically has not sufficiently and effectively removed foreign matter or particulates. The prior art wafers have also commonly had planar surfaces, relying upon deformation of these surfaces when in contact with surfaces to be cleaned by them. The deformation is often accomplished by applying a vacuum, forcing the compressible cleaning wafer to deform against a mating surface of the surface to be cleaned by the cleaning wafer.
Also available are off-line cleaning methods such as use of a grindstone abrasion (ASML) combined with vacuum based particle collection to remove debris remaining after using the previously described cleaning wafer techniques. This type of cleaning process is an add-on feature at considerable cost. The grindstone cleaning also typically requires tool downtime and opening of the automated wafer handling equipment.